1. Field of the Invention
The embodiments of the invention generally relate to complementary metal oxide semiconductor (CMOS) devices and, more particularly, to an improved method for forming p-type and n-type, multi-gated, non-planar, field effect transistors (MUGFETs) with high mobility crystalline semiconductor fins in high-density, chevron-patterned, CMOS devices.
2. Description of the Related Art
Integrated circuit design decisions are often driven by device scalability and manufacturing efficiency. For example, as the size of planar field effect transistors (planar FETs) is reduced, generally so is the drive current. In response, MUGFETs, such as fin-type FETs (FINFETs) or trigate FETs, were developed to provide scaled devices with faster drive currents and reduced short channel effects.
Integrated circuit design decisions are also driven by a desire for improved performance, such as a desire to reduce device delay. For example, in both NFETS and PFETs, charge carrier mobilities effect delay. These charge carrier mobilities can be a function of the crystalline orientation of the semiconductor material used to form the FET channel region. Recent developments in MUGFET technology allow semiconductor fins having different crystalline orientations to be formed on the same substrate. For example, semiconductor fins can be formed in a chevron pattern from a [100] crystalline orientation semiconductor layer such that the semiconductor fins on opposite sides of the chevron have different crystalline orientations (e.g., [100] crystalline orientation and [110] crystalline orientation, respectively). The [100] crystalline orientation semiconductor fins can be incorporated into NFETs for optimal electron mobility, whereas the [110] crystalline orientation semiconductor fins can be incorporated into PFETs for optimal hole mobility. However, due to the different fin angles (i.e., due to the chevron pattern), CMOS devices with such high mobility semiconductor fins are subject to unique density and scalability issues as compared to conventional CMOS devices.